AMD wants to make the L2 cache in its processors gigantic too
The success of 3D V-Cache technology is driving AMD forward. According to a new patent and research paper titled Balanced Latency Stacked Cache, the company is now exploring ways to stack the second-level cache (L2) vertically.
The L2 cache is much faster than the L3 and is located much closer to the computing cores. Traditionally, increasing the cache size leads to increased latency, as the signal has to travel a greater distance across the chip, but vertical stacking solves this problem.
According to AMD's calculations, the use of a 1 MB "three-dimensional" L2 reduces access time from 14 cycles (in a planar design) to 12 cycles. The patent describes an architecture where connections (TSVs) pass through the center of the stack. This provides "balanced latency" — data is delivered to all cache layers at the same speed.
While 3D V-Cache for L3 gave a huge boost in games by reducing RAM accesses, L2 stacking can increase IPC (instructions per clock) in all types of tasks. Faster and larger L2 is critical for workloads that are sensitive to the speed of data exchange within the core.